CSCI 2150 -- Laboratory Experiment 8
LabView: Chip Select Design

The purpose of this lab is to give you an opportunity to design chip selects. I realize that the lecture did not go smoothly for everyone, so hopefully this lab will compensate.

I have designed a LabView virtual instrument that takes a hexadecimal number and breaks it into its individual bits. This program should be stored in each of your computers at C:\CSCI2150\Chipsel.vi. The front panel to this VI is shown below.

The address input is the sole input of the panel. In it, you can input a value from 0000₁₆ to FFFF₁₆. The row of LEDs labeled A0, A1, A2, ... A15 represent the individual bits of the hexadecimal number. You will notice that the number D324₁₆ is displayed which results in the binary value 1101 0011 0010 0100₂ that is displayed on the LEDs.

In addition, you will notice that there are three LEDs at the bottom of the panel labeled CS1, CS2, and CS3. These are the outputs that you are going to create the software for.

As for the diagram, you get the little bit of wiring I did to break the hex value into bits, the individual bits A0 through A15 that you will use to create the chip selects, and the chip select outputs CS1, CS2, and CS3. The diagram is shown below.

Your job, plain and simple, will be to design the logic for the three chip selects so that the memory range for each chip select is equal to that shown below.

Once you've designed the chip selects, you will be able to test them using the LabView virtual instrument.

Chip Select Review

The need for memory mapping (assigning different components of memory to different portions of the memory map) arises from the need to have multiple memory devices accessible across a single address/data bus.  Therefore, we need to have a method of setting the "base" or "starting" address of a memory device to an address other than 0.  For example, the memory map below has a ROM starting at address 0x1000, a RAM starting at 0x4000, and a piece of memory-mapped I/O starting at address 0xC000.

Let's start by reviewing the basic structure of a memory chip.  The figure below shows the basic components of a memory chip.

It has n input address lines, therefore, the size of the memory is 2ⁿ. It has m data lines, and therefore can store m bits of data for each address. The main lines of control for the memory are ^R, ^W, and ^CS.  When ^R is low, the processor is reading from the memory and the memory should be outputting data on its data lines. When ^W is low, then the processor is writing data and the memory should be inputting data to store in the memory cells.

If ^CS is high, the data lines of the chip are disabled.  It is as if the chip is not even connected.  When ^CS is low, the data lines are enabled for input or output based on the state of ^R and ^W.  It is this ^CS line that enables multiple devices to be connected to a single set of data lines as shown in the image below.

As far as the processor is concerned, it has n output address lines where this n must be at least as large and most likely larger than the n input address lines to the memory chip.  In this case, n gives you the size of your memory space (the number of memory locations addressable by the processor) and is once again calculated as 2ⁿ. It also has m labeled D₀ through D_m-1 where m is the number of bits of data. This m should be the same value as the m on the memory chips.

Creating a Chip Select

Assume we have a 1 Meg address space.  (I.e., the processor can address up to 1,048,576 memory spaces.)  How many address lines does the processor have?

Assume we want to insert a 64K (65,536 memory addresses) RAM starting at address 0x48000.  First, how many address lines does the 64K memory chip have?

First, convert the hexadecimal low address of 0x48000 to binary.

Now, divide the processor's address lines into the addresses that will be input to the memory and the addresses that will be used to create the chip select.

Okay, so we have a problem. A₁₅ is a one for the lowest address, but since it is one of the address lines to the memory chip, its low address value MUST BE A ZERO.

Therefore, the low address of the 64K memory chip must either be incremented so that it goes to the next address where A₀ through A₁₅ all equal zeros or decremented to the first address below 0x48000 where A₀ through A₁₅ all equal zeros.  These two options are shown below.

Let's pick the next highest address, binary 0101 0000 0000 0000 0000 which equals 0x50000 in hexadecimal.  What will be the 64K memory's highest address?  Well, it will be the address where all of the address lines, A₀ through A₁₅, are one.  That value is binary 0101 1111 1111 1111 1111 which equals 0x5FFFF in hexadecimal.  The resulting memory map is shown below.

We now need to make a chip select that is a logic zero only when A₁₉ = 0, A₁₈ = 1, A₁₇ = 0, and A₁₆ = 1.  Using a NAND gate as we have in class for the 1-of-x selectors, we get:

Designing the Chip Selects

Now let's get back to designing the chip selects for this lab. I want you do to five things:

• determine the memory space of the microprocessor with 16 address lines;
• determine the size of each of the blocks of memory defined with the chip selects;
• verify that the starting address is valid for each of the memory blocks;
• design the chip selects; and
• implement them in LabView to prove that your design works.

Once you have finished your LabView circuits, call me over to verify their operation.

Happy programming!

Developed by David Tarnoff for the Spring 2001 sections of CSCI 2150 at ETSU