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Ports, Interrupts, and DMA

Reading: Digital Fundamentals sections 14-7 through 14-9

Memory Mapping

Before Test 2, we discussed locating devices in an area of the memory map by using chip selects. The basic format had the address lines of least significance going to that address inputs of the chip and the address lines of higher significance going to drive the chip select. An active low ^R signal to indicate when data is being read from the memory and an active low ^W signal to indicate when data is being sent/written to the device. Data lines pass the actual data between the memory and the processor.

Memory mapping is similar in that a chip select tells the device when it's being accessed and data lines pass data between the device and the processor. Memory mapped I/O, however, does not usually have address lines going directly to the chip, and only chips that can both input and output (bidirectional I/O) use both the ^R and ^W lines.

You may use as many address lines as you wish to isolate the chip select, just beware that EVERY address in the range defined for that chip select reads or writes to the same device.

IMPORTANT: Intel doesn't use the ^R and ^W notation to label their read and write lines Instead, it uses the label ^MRDC for read and ^MWTC for write.

Examples of hardware used to interface to ports

Be sure to print out the first page only of the following data sheets:

  • Memory-mapped output -- uses a latch such as the 74HC574
  • Memory-mapped input -- uses an input buffer such as the 74HC541
  • Memory-mapped bidirectional -- uses a bus transceiver such as the 74HC245

Differences between I/O ports and memory

The Intel processors have a "second bus" that operates in parallel with the memory interface. In fact, it uses the same address and data lines that make up the memory bus. There are slight differences, however, that make the operation of these two buses different for interfacing to I/O devices.

I/O ports

  • I/O ports use a line similar to ^MRDC called ^IORC to read from I/O devices. The signal operates the same way as ^MRDC in that it goes low when data is supposed to come into the processor. The difference is that it reads data with the assembly language instructions IN and INS rather than MOV.
  • I/O ports use a line similar to ^MWTC called ^IOWC to write data to I/O devices. The signal operates the same way as ^MWTC in that it goes low when data is supposed to be sent from the processor to the I/O devices. The difference is that it writes data with the assembly language instructions OUT and OUTS rather than MOV.
  • I/O ports only use the first 16 address lines for addressing and chip selects.

Memory mapped I/O

  • Memory mapped I/O uses the Intel lines ^MWTC to perform a write (output) to the device and ^MRDC to perform a read (input). These lines correspond to passing data with the assembly language instruction MOV.
  • Memory mapped I/O uses the full set of address lines for addressing and chip selects.

Passing Data to/from Peripherals

There are two ways to pass data back an forth between peripherals.

  • Polling -- processor goes to device and asks it if it has data to send
  • Interrupts -- device "calls" processor, interrupting it from the program it is running, in order to service the data

There are two types of interrupts

  • Device interrupts -- The device external to the processor forces the interrupt. There are multiple interrupts of this type.
  • Software interrupts -- The processor can force an interrupt to be called by executing an instruction called a software interrupt (assembly language command INT)

Why do we need interrupts? Well, the processor wouldn't want to constantly be checking the PC keyboard during a long computation. It would only slow things up. But if the keyboard could interrupt the processor only when a key press is available, then the processor could focus on more important things.

Another use for interrupts could be for things like a network interface. If a network card has a buffer of data that is about to become full, it can interrupt the processor so that no data is lost to overflows.

The format of an interrupt is a lot like that of a subroutines (or method or function if you wish). The difference is that the main program does not have to "call" them. They are called automatically by the CPU without affecting the main code. These "subroutines" are called Interrupt Service Routines (ISR).

When the interrupt is called, the ISR can then pass data to and from the device just like communicating with memory.

A programmable interrupt controller (PIC) maintains the interrupts by providing two things to the processor.

  • It prioritizes the interrupts so that if two occur at the same time, the most important one is serviced first
  • It maintains a list of the addresses where the interrupt service routines are located and a reference indicating which ISR services which interrupt.

Direct Memory Access

Up to now, we have discussed memory-to-register transfers, register-to-register transfers, and register-to-memory transfers. Each of these methods involve passing data to or from the registers. If, however, we have to pass a piece of data between two portions of memory, the code would look something like this:

mov ax,[source address]
mov [destination address],ax

Two steps to move data from one place to another in memory. This is not a big problem for small amounts of data, but if we have a large block to transfer, the added transfer causes a significant delay.

Direct Memory Access (DMA) bypasses the register by transferring data directly from one memory device to another. For example, to load a program from the hard drive to memory, DMA bypasses the processor and transfers the data directly. Figures 14-37 and 14-38 in your textbook represent this process quite well.

Notes developed by David Tarnoff solely for use by students in his sections of CSCI 2150.