Okay, we've covered alot of material since the start of the semester, and although much of it has been of the "discussion" nature, e.g., how might the size of a cache affect the speed of a small application, some of it has also been computational in nature. Below you will find a list of the topics that will be covered on Test 1. Included for each topic is the reading from the textbook for that topic. I've also tried to put together a list of the questions from previous year's tests that address that topic. You can find copies of those tests from the following links.
I would look for the test to be about 60% to 70% short answer questions such as "For a specific block size, which cache uses the most bits in a tag?" (BTW, the answer is full associative.) The remaining portion of the test will be questions longer questions such as:
Topic | Reading | Class Notes | Class Exercises |
Hardware/Software/Firmware Allocation | N/A -- See slides | Lecture slides | Last slide of lecture |
Functional View/History | Sections 1.2, 2.1, & 2.3 | Lecture slides | Slide 14 of lecture |
Performance | Section 2.2 | Lecture slides | Slide 20 of lecture |
Single Processor Architecture and Interrupts | Sections 3.1 through 3.3 | Lecture slides | Single Processor Architecture Quiz |
Memory Hierarchy | Chapter 4 | Lecture slides | N/A |
RAM Caches | Chapter 4 |
Lecture slides Worksheets |
Slides 20, 21, 27, 32, and 34 from lecture Memory Hierarchy and Cache Quiz |
Buses | Sections 3.4, 3.5, & 7.7 | Lecture slides (1-9, 12-19, 21, 22, 30-40) | See the PCI discussion on D2L |
Memory Details | Sections 5.1 and 5.3 |
Lecture slides (13-34) Worksheets |
N/A |
Error Detection and Correction | Section 5.2 |
Lecture slides Worksheets |
SEC/DED Assignment |
Memory Management | Sections 8.3 and 8.4 | Lecture slides (1-33 and 40-46) | Slide 33 from lecture |
Below is a mapping of previous year's tests to questions that might look good for this first test of ours.
Topic | Fall '05 Test 1 | Fall '06 Test 1 | Fall '05 Test 2 | Fall '06 Test 2 | Fall '05 Test 3 |
HW/SW/FW Allocation | 1 | 1 | |||
Functional View/History | 2, 3 | 2 | |||
Performance | 5, 6, 11, 12 | 3, 4, 9 | |||
Single Processor Arch/Interrupts | 7-10, 13, 14 | 5-8, 11, 12, 28, 29 | |||
Memory Hierarchy/RAM Caches | 15-32 | 13-25 | |||
Buses | 27-42 | 22-36 | |||
Memory Details | 33-37 | 10, 26, 27, 30 | |||
Error Correction | 31-36 | 1-10 | |||
Memory Management | 1-7 |